Static Random Access Memory (SRAM) is widely used in areas such as personal computers, personal communications, and consumer electronics products (e.g., digital cameras).
FIGS. 1-2 respectively depict a circuit diagram and a plan view of a conventional memory cell in a six-transistor (6T) SRAM memory. The memory cell includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3 and a fourth NMOS transistor N4. The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transistor N2 form a bistable circuit. The bistable circuit forms a latch for latching data information. The first PMOS transistor P1 and the second PMOS transistor P2 are pull-up transistors. The first NMOS transistor N1 and the second NMOS transistor N2 are pull-down transistors. The third NMOS transistor N3 and the fourth NMOS transistor N4 are transfer transistors.
A gate of the first PMOS transistor P1, a gate of the first NMOS transistor N1, a drain of the second PMOS transistor P2, a drain of the second NMOS transistor N2 and a source of the fourth NMOS transistor N4 are electrically connected to form a first storage node 11. A gate of the second PMOS transistor P2, a gate of the second NMOS transistor N2, a drain of the first PMOS transistor P1, a drain of the first NMOS transistor N1, and a source of the third NMOS transistor N3 are electrically connected to form a second storage node 12. Gates of the third NMOS transistor N3 and the fourth NMOS transistor N4 are electrically connected to a word line WL. A drain of the third NMOS transistor N3 is electrically connected to a first bit line BL. A drain of the fourth NMOS transistor N4 is electrically connected to a second bit line (complementary bit line) BLB. A source of the first PMOS transistor P1 and a source of the second PMOS transistor P2 are electrically connected to a power supply line Vdd. A source of the first NMOS transistor N1 and a source of the second NMOS transistor N2 are electrically connected to a ground line Vss.
When the SRAM memory is in a read operation, a current flows from the first bit line BL and the second bit line BLB that are at a high voltage level to the first storage node 11 or the second storage node 12 that is at a low voltage level. When the SRAM memory is in a write operation, a current flows from one of the first storage node 11 and the second storage node 12 that is at a high voltage level to one of the first bit line BL and the second bit line BLB that is at a low voltage level.
In conventional technologies, in order to connect a gate, a source or a drain of a transistor, a connection plug is usually provided on top of the gate, the source or the drain. The connection plug is used to lead out the gate, the source, or the drain for connecting with another device.
FIG. 3 depicts a cross-sectional view of a transistor used in a conventional SRAM memory. The transistor includes a semiconductor substrate 10, and a gate formed on the semiconductor substrate 10. The gate includes a gate dielectric layer 116B, a gate electrode layer 118B and a contact layer 119B that are sequentially formed on the semiconductor substrate 10. The gate also includes sidewalls 122B formed on both sides of the gate dielectric layer 116B, the gate electrode layer 118B and the contact layer 119B. The transistor also includes a connection plug G formed on top of the gate electrode layer 118B. The connection plug G is formed in an interlayer dielectric layer 104 and is for leading out the gate electrode layer 118B of the transistor. However, the connection plug G occupies a relatively large portion of a space between transistors. Corresponding SRAM memories are thus generated with large sizes.